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SERIAL PRESENCE DETECT
PC133 Unbuffered DIMM
PC133 Single Sided Unbuffered SDRAM DIMM(168pin) SPD Specification
REV. 1.3 March. 2000
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S0424DTS-C75(Intel SPD 1.2B ver. base)
U U
PC133 Unbuffered DIMM
U
U
U
U
U
U
Organization : 4Mx64 Composition : 4Mx16 *4 Used component part # : K4S641632D-TC75 # of rows in module : 1 row # of banks in component : 4 banks Feature : 1,000mil height & double sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 8 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x16 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 32MB 1.5ns 0.8ns 1.5ns 00h 00h 00h 00h 14h 0Fh 14h 2Dh 08h 15h 08h 15h 2 2 0Eh Hex value -75 80h 08h 04h 0Ch 08h 01h 40h 00h 01h 75h 54h 00h 80h 10h 00h 01h 8Fh 04h 04h 01h 01h 00h 2 2 1 1 Note
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h 9Bh CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 30h 34h 32h 34h 44h 54h 53h 2Dh 43h 37h 35h 20h 53h 44h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 0 4 2 4 D T S "-" C 7 5 Blank S D-die (5th Gen.) Undefined 100MHz Detailed 100MHz Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S0823DTS-C75(Intel SPD 1.2B ver. base)
U U
PC133 Unbuffered DIMM
U
U
U
U
U
U
Organization : 8Mx64 Composition : 8Mx8 *8 Used component part # : K4S640832D-TC75 # of rows in module : 1 row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 9 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 64MB 1.5ns 0.8ns 1.5ns 00h 00h 00h 00h 14h 0Fh 14h 2Dh 10h 15h 08h 15h 2 2 0Eh Hex value -75 80h 08h 04h 0Ch 09h 01h 40h 00h 01h 75h 54h 00h 80h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h 2 2 1 1 Note
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h 9Ch CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 30h 38h 32h 33h 44h 54h 53h 2Dh 43h 37h 35h 20h 53h 44h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 0 8 2 3 D T S "-" C 7 5 Blank S D-die (5th Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M374S0823DTS-C75(Intel SPD 1.2B ver. base)
U U
PC133 Unbuffered DIMM
U
U
U
U
U
U
Organization : 8Mx72 Composition : 8Mx8 *9 Used component part # : K4S640832D-TC75 # of rows in module : 1 row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 9 1 row 72 bits LVTTL 7.5ns 5.4ns ECC 15.625us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time 20ns 15ns 20ns 45ns 1 row of 64MB 1.5ns 0.8ns 1.5ns 00h 00h 00h 00h 14h 0Fh 14h 2Dh 10h 15h 08h 15h 2 2 Hex value -75 80h 08h 04h 0Ch 09h 01h 48h 00h 01h 75h 54h 02h 80h 08h 08h 01h 8Fh 04h 04h 01h 01h 00h 2 2 1 1 Note
22
SDRAM device attributes : General
0Eh
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h AEh CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 30h 38h 32h 33h 44h 54h 53h 2Dh 43h 37h 35h 20h 53h 44h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 7 4 S 0 8 2 3 D T S "-" C 7 5 Blank S D-die (5th Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S0924BTS-C75(Intel SPD 1.2B ver. base)
U U
PC133 Unbuffered DIMM
U
U
U
U
U
U
Organization : 8Mx64 Composition : 8Mx16 *4 Used component part # : K4S281632B-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,000mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 9 1 Row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x16 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 Row of 64MB 1.5ns 0.8ns 1.5ns 00h 00h 00h 00h 14h 0Fh 14h 2Dh 10h 15h 08h 15h 2 2 0Eh Hex value -75 80h 08h 04h 0Ch 09h 01h 40h 00h 01h 75h 54h 00h 80h 10h 00h 01h 8Fh 04h 04h 01h 01h 00h 2 2 1 1 Note
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h A4h CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 30h 39h 32h 34h 42h 54h 53h 2Dh 43h 37h 35h 20h 53h 42h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 0 9 2 4 B T S "-" C 7 5 Blank S B-die (3rd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S0924CTS-C75(Intel SPD 1.2B ver. base)
U U
PC133 Unbuffered DIMM
U
U
U
U
U
U
Organization : 8Mx64 Composition : 8Mx16 *4 Used component part # : K4S281632C-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,000mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 9 1 Row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x16 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 Row of 64MB 1.5ns 0.8ns 1.5ns 00h 00h 00h 00h 14h 0Fh 14h 2Dh 10h 15h 08h 15h 2 2 0Eh Hex value -75 80h 08h 04h 0Ch 09h 01h 40h 00h 01h 75h 54h 00h 80h 10h 00h 01h 8Fh 04h 04h 01h 01h 00h 2 2 1 1 Note
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h A4h CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 30h 39h 32h 34h 43h 54h 53h 2Dh 43h 37h 35h 20h 53h 43h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 0 9 2 4 C T S "-" C 7 5 Blank S C-die (4th Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S1723ATS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 16Mx64 Composition : 16Mx8 *8 Used component part # : K4S280832A-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 10 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Ch 0Ah 01h 40h 00h 01h 75h 54h 00h 80h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 128MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 20h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h ADh CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 31h 37h 32h 33h 41h 54h 53h 2Dh 43h 37h 35h 20h 53h 41h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 1 7 2 3 A T S "-" C 7 5 Blank S A-die (2nd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S1723BTS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 16Mx64 Composition : 16Mx8 *8 Used component part # : K4S280832B-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 10 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Ch 0Ah 01h 40h 00h 01h 75h 54h 00h 80h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 128MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 20h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h ADh CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 31h 37h 32h 33h 42h 54h 53h 2Dh 43h 37h 35h 20h 53h 42h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 1 7 2 3 B T S "-" C 7 5 Blank S B-die (3rd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S1723CTS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 16Mx64 Composition : 16Mx8 *8 Used component part # : K4S280832C-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 10 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 15.625us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Ch 0Ah 01h 40h 00h 01h 75h 54h 00h 80h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 128MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 20h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h ADh CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 31h 37h 32h 33h 43h 54h 53h 2Dh 43h 37h 35h 20h 53h 43h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 1 7 2 3 C T S "-" C 7 5 Blank S C-die (4th Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M374S1723ATS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 16Mx72 Composition : 16Mx8 *9 Used component part # : K4S280832A-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 10 1 Row 72 bits LVTTL 7.5ns 5.4ns ECC 15.625us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 Row of 128MB 1.5ns 0.8ns 1.5ns
Hex value -75 80h 08h 04h 0Ch 0Ah 01h 48h 00h 01h 75h 54h 02h 80h 08h 08h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 20h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h BFh CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 31h 37h 32h 33h 41h 54h 53h 2Dh 43h 37h 35h 20h 53h 41h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 7 4 S 1 7 2 3 A T S "-" C 7 5 Blank S A-die (2nd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M374S1723BTS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 16Mx72 Composition : 16Mx8 *9 Used component part # : K4S280832B-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 10 1 Row 72 bits LVTTL 7.5ns 5.4ns ECC 15.625us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 Row of 128MB 1.5ns 0.8ns 1.5ns
Hex value -75 80h 08h 04h 0Ch 0Ah 01h 48h 00h 01h 75h 54h 02h 80h 08h 08h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 20h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h BFh CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 31h 37h 32h 33h 42h 54h 53h 2Dh 43h 37h 35h 20h 53h 42h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 7 4 S 1 7 2 3 B T S "-" C 7 5 Blank S B-die (3rd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M374S1723CTS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 16Mx72 Composition : 16Mx8 *9 Used component part # : K4S280832C-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 12 10 1 Row 72 bits LVTTL 7.5ns 5.4ns ECC 15.625us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 Row of 128MB 1.5ns 0.8ns 1.5ns
Hex value -75 80h 08h 04h 0Ch 0Ah 01h 48h 00h 01h 75h 54h 02h 80h 08h 08h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 20h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h BFh CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 31h 37h 32h 33h 43h 54h 53h 2Dh 43h 37h 35h 20h 53h 43h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 7 4 S 1 7 2 3 C T S "-" C 7 5 Blank S C-die (4th Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S3253ATS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 32Mx64 Composition : 32Mx8 *8 Used component part # : K4S560832A-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 8K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 13 10 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 7.8us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Dh 0Ah 01h 40h 00h 01h 75h 54h 00h 82h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 256MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 40h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h D0h CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 33h 32h 35h 33h 41h 54h 53h 2Dh 43h 37h 35h 20h 53h 41h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 3 2 5 3 A T S "-" C 7 5 Blank S A-die (2nd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M366S3253BTS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 32Mx64 Composition : 32Mx8 *8 Used component part # : K4S560832B-TC75 # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 8K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 13 10 1 row 64 bits LVTTL 7.5ns 5.4ns Non parity 7.8us, support self refresh x8 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Dh 0Ah 01h 40h 00h 01h 75h 54h 00h 82h 08h 00h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 256MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 40h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h D0h CEh 00h 01h 4Dh 33h 20h 36h 36h 53h 33h 32h 35h 33h 42h 54h 53h 2Dh 43h 37h 35h 20h 53h 42h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 6 6 S 3 2 5 3 B T S "-" C 7 5 Blank S B-die (3rd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M374S3253ATS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 32Mx72 Composition : 32Mx8 *9 Used component part # : K4S560832A-TC75 # of rows in module : 2 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 8K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 13 10 1 row 72 bits LVTTL 7.5ns 5.4ns ECC 7.8us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Dh 0Ah 01h 48h 00h 01h 75h 54h 02h 82h 08h 08h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 256MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 40h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h E2h CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 33h 32h 35h 33h 41h 54h 53h 2Dh 43h 37h 35h 20h 53h 41h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 7 4 S 3 2 5 3 A T S "-" C 7 5 Blank S A-die (2nd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
M374S3253BTS-C75(Intel SPD 1.2B ver. base)
* * * * * * * * Organization : 32Mx72 Composition : 32Mx8 *9 Used component part # : K4S560832B-TC75 # of rows in module : 2 Row # of banks in component : 4 banks Feature : 1,375mil height & single sided Refresh : 8K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuration type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes
PC133 Unbuffered DIMM
Function Supported -75 128bytes 256bytes (2K-bit) SDRAM 13 10 1 row 72 bits LVTTL 7.5ns 5.4ns ECC 7.8us, support self refresh x8 x8 tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 3 0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
Hex value -75 80h 08h 04h 0Dh 0Ah 01h 48h 00h 01h 75h 54h 02h 82h 08h 08h 01h 8Fh 04h 04h 01h 01h 00h
Note
1 1
2 2
22 23 24 25 26 27 28 29 30 31 32 33 34
SDRAM device attributes : General SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
Burst Read Single bit Write precharge all, auto precharge 20ns 15ns 20ns 45ns 1 row of 256MB 1.5ns 0.8ns 1.5ns
0Eh 00h 00h 00h 00h 14h 0Fh 14h 2Dh 40h 15h 08h 15h 2 2
REV. 1.3 March. 2000
SERIAL PRESENCE DETECT
Byte # 35 36 37~60 61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described Data signal input hold time Superset information (maybe used in future) Superset information (maybe used in future) Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations -75 0.8ns -
PC133 Unbuffered DIMM
Function Supported Hex value -75 08h 00h 00h 00h 12h E2h CEh 00h 01h 4Dh 33h 20h 37h 34h 53h 33h 32h 35h 33h 42h 54h 53h 2Dh 43h 37h 35h 20h 53h 42h 64h ADh 3 3 4 Note
Intel Rev 1.2B Samsung Samsung Onyang Korea M 3 Blank 7 4 S 3 2 5 3 B T S "-" C 7 5 Blank S B-die (3rd Gen.) Undefined 100MHz Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
REV. 1.3 March. 2000

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